1. Field of the Invention
The present invention relates generally to the field of semiconductor fabrication and more particularly to methods for utilizing metrology to improve dimensional uniformity during processing both across wafers and between wafers.
2. Description of the Prior Art
Semiconductor fabrication is commonly performed on substrates such as wafers of single-crystal silicon. Typically, numerous identical devices are fabricated on each wafer, and accordingly, one goal of semiconductor fabrication technology is to ensure uniformity between devices made at different locations on a wafer as well as uniformity between devices produced on different wafers. Ensuring such uniformity across and between wafers requires uniformity in processing so that, for example, layers have uniform and repeatable thicknesses and features have consistent dimensions. Unfortunately, deviations caused by non-uniform processing in one processing step can often become magnified through subsequent processing steps. Thus, if a deposited material layer varies in thickness across a wafer, a specific feature defined from that layer can have varying dimensions in different devices formed at different locations on that wafer.
Additionally, semiconductor processing is typically performed under high vacuum in very clean environments. In order to minimize contamination of wafers, multiple processing chambers are commonly clustered together with robotic means that are configured to shuttle wafers between the various chambers. In this way repetitive processes such as depositing layers, masking, etching, stripping, cleaning, and annealing can be performed on a wafer without exposing the wafer to the outside environment.
In order to control processing steps during semiconductor processing it is sometimes necessary to remove one or more test wafers from the processing cluster for either destructive or non-destructive measurement. One common destructive measurement technique is to cross-section a wafer to allow fabricated features to be observed in profile with a metrology tool such as a scanning electron microscope (SEM). This technique can provide highly accurate measurements of heights, widths, sidewall angles, radii of curvature, layer thicknesses, and so forth. This technique, however, destroys the wafer and is very time consuming and expensive to perform for each sample area being investigated. Another destructive technique employs focused ion-beam (FIB) milling to essentially define a low-angle trench into the wafer at a desired location. Like cross-sectioning, this technique allows features to be viewed in profile in a SEM, however, the profile is at a low angle and therefore certain measurements have to be corrected to account for the angle. While FIB allows more locations on a wafer to be investigated more rapidly, the wafer nevertheless is destroyed.
Several non-destructive techniques also exist. One such technique uses SEM to view features on a wafer from above, rather than in profile as with a cross-section. While this technique does not destroy the wafer, and can allow the wafer to be put back into the processing stream, it may increase wafer contamination, it can be time consuming to remove the wafer from the processing environment, and provides only limited measurements. Principally, this technique is used to measure lateral dimensions, such as line widths, but does not provide information about layer thicknesses, sidewall angles, and the like.
Another non-destructive technique involves ellipsometry which measures properties of light reflected at a low angle from a surface. Ellipsometry is well suited for measuring layer thicknesses of materials that are at least partially transparent to the selected wavelength of light, however, this technique measures a fairly large area compared to the dimensions of specific features produced in semiconductor fabrication. Thus, ellipsometry cannot be used to measure individual features on a wafer.
Because of the limitations of the available measurement techniques, semiconductor processing is commonly controlled by periodically measuring one or a few areas on selected wafers and applying those measurements to all subsequent wafers until another round of measurements is performed. As an example, the length of time of an etching step may depend on the thickness of a photoresist layer. To determine the correct etch time, the photoresist layer on a test wafer is measured in several locations and averaged. That average is then used to select the etch time for a number of subsequent wafers. It will be appreciated that variations from the average in the photoresist thickness across a wafer and between wafers can cause both over-etching and under-etching when a consistent etch time is used. It will be further appreciated that other processing steps can have similar dependencies such that applying a uniform processing condition based on a single measurement, or even an average of measurements, can produce inconsistent results across and between wafers.
Therefore, what is desired is a method for non-destructively measuring every wafer undergoing semiconductor processing to tailor subsequent processing steps to improve uniformity across and between wafers.